A Practical Guide to Debugging with JTAG

When a new hardware prototype is dead on the bench, every minute your team spends guessing at the problem is a direct hit to your project schedule and budget. Unstructured debugging during board bring-up leads to expensive board respins and cascading delays that are often entirely preventable. This is a critical failure point, especially during the high-stakes transition from EVT to DVT.

This guide is for engineering leaders, program managers, and principal engineers responsible for shipping complex electronics on time. It focuses on the operational impact of JTAG debugging—how it de-risks hardware bring-up, accelerates firmware development, and preserves your time-to-market. We won’t get lost in the IEEE 1149.1 standard; this is a practical manual for using JTAG to solve the real-world problems that derail product launches. The recommendation is clear: a disciplined JTAG workflow is non-negotiable for predictable program execution.

By the end of this guide, you will learn how to:

• Diagnose and fix the most common physical and logical JTAG connection failures.
• Structure your toolchain configuration for repeatable, efficient debugging sessions.
• Apply core JTAG techniques to solve complex hardware and firmware issues with speed.

Why JTAG is a Mission-Critical Capability

From a program management perspective, debugging with JTAG is fundamentally about risk reduction. Every day a board remains non-functional is a day of lost engineering productivity and a step closer to a schedule slip. An effective JTAG workflow compresses the diagnostic timeline from days or weeks down to hours, turning unknowns into actionable data. This is a core competency for any team aiming to ship reliable hardware.

The market reflects this strategic importance. The JTAG Boundary Scan Hardware market was valued at $929.175 million in 2021 and is projected to exceed $1.3 billion by 2025. This growth is driven by the increasing complexity of modern electronics and the non-negotiable need for robust testability in every System on Chip (SoC) design.

Adopting a “design for testability” mindset by incorporating accessible JTAG ports from the first prototype is a hallmark of high-performing engineering teams. It’s a strategic investment that pays dividends throughout the product lifecycle, from initial bring-up to manufacturing test and field failure analysis.

Ultimately, JTAG is more than a debug tool; it’s a program execution tool. It provides the visibility required to de-risk hardware bring-up, stabilize firmware, and move from prototype to production with confidence. Forgoing this capability is a choice to accept preventable delays and costs as part of your development process.

Establishing a Rock-Solid JTAG Connection

Nothing grinds a hardware bring-up session to a halt faster than a flaky JTAG connection. A bad connection can send an engineering team down a rabbit hole for hours, burning valuable time and morale. The goal is to make the connection so reliable that you forget it’s there, allowing the team to focus on finding firmware bugs, not fighting the tools. This requires rigorous attention to the physical interface, probe selection, and signal integrity.

Getting the Physical Hookup Right

The first step is correctly identifying the core JTAG signals on your board. There are four mandatory signals:

• TDI (Test Data In): Sends data and instructions into the target chip’s JTAG logic.
• TDO (Test Data Out): The return path where data shifts out of the target, allowing you to read device states.
• TCK (Test Clock): The heartbeat of the interface, synchronizing all operations. Its frequency dictates the data rate.
• TMS (Test Mode Select): Directs the JTAG state machine—the Test Access Port (TAP) controller—to perform specific actions.

An optional fifth signal, TRST (Test Reset), asynchronously resets the TAP controller. A common failure mode is leaving this pin floating or improperly handled, which can prevent the JTAG state machine from initializing correctly. Verifying these connections is the first diagnostic step.

Investing a few minutes upfront to validate the physical layer directly reduces project risk and saves budget.

A stable debugging setup isn’t just a technical win; it’s a direct investment in program predictability and successful execution.

Choosing Your JTAG Debug Probe

The debug probe is the physical bridge between your development workstation and the target hardware. The choice of probe directly impacts debugging speed, reliability, and engineering efficiency.

Options range from inexpensive FTDI-based adapters to professional-grade tools like a SEGGER J-Link or a Lauterbach TRACE32. For serious product development, a professional probe is a crucial investment in productivity.

JTAG Debug Probe Comparison

The Recommendation: While it’s tempting to use a low-cost adapter, this is often a false economy. I have seen teams save $200 on a probe only to have two engineers burn an entire day fighting a flaky connection, resulting in thousands of dollars in lost productivity and schedule delays. For any commercial product, a professional-grade probe like a J-Link is the correct business decision. These considerations are a key part of our approach to PCB design for manufacturing.

Ensuring Signal Integrity

Even with a high-quality probe, a noisy connection will cripple your debugging efforts. The number one rule is to keep the ribbon cable between the probe and target as short as possible (ideally under 15 cm). Long cables act as antennas, picking up noise that corrupts signals, especially at higher TCK speeds.

Proper grounding and voltage referencing are equally critical. Your board’s JTAG connector must have a pin for the target’s VCC (often labeled Vref or Vtarget). The probe uses this to set its I/O logic levels. A missing ground or a poorly connected Vref is a frequent cause of unstable connections and can even damage the target or probe.

Before the IEEE 1149.1 standard was established in 1990, engineers had to use logic analyzers to manually probe every pin on a chip. That painstaking process drove the industry to create the standardized Test Access Port we rely on today. For more on how this standard revolutionized circuit testing and debugging, check out this article on Truechip.net.

With a stable physical connection, the next step is configuring the software toolchain—typically OpenOCD (Open On-Chip Debugger) and GDB (GNU Debugger)—to communicate with the target.

This software setup is the brain of your JTAG operation, translating high-level debug commands into the low-level electrical signals that control the processor.

Decoding the OpenOCD Configuration

OpenOCD uses simple text-based configuration files (.cfg) to define the debug session. A best practice is to break the configuration into logical, reusable parts rather than using a single monolithic file. This modular approach makes the setup easier to manage and troubleshoot.

A standard configuration sequence involves three steps:

1. Source the Interface/Adapter File: Tells OpenOCD which JTAG probe you are using (e.g., SEGGER J-Link, ST-LINK).
2. Source the Target CPU File: Provides specifics for your MCU or SoC, including its JTAG TAP ID, memory map, and core architecture (e.g., Cortex-M4, RISC-V).
3. Set the Transport Protocol: Explicitly state you’re using JTAG. Even though many ARM cores also support SWD, being specific eliminates ambiguity.

This structured approach avoids reinventing the wheel and is a key practice for building a robust, repeatable verification strategy.

Real-World Scenario: STM32H7 Bring-Up

Problem: A new medical device prototype using an STM32H7 MCU fails to boot. The screen is black, and there are no serial logs. The firmware team is blocked.
Stakes: Each day of delay costs over $10,000 in burn rate and pushes the DVT entry date, risking a multi-week slip in the product launch.

Solution: Use JTAG for direct hardware-level diagnosis. The lead engineer creates a simple openocd.cfg file:

# Source the interface configuration for our J-Link probe.
source [find interface/jlink.cfg]

# Specify the transport protocol.
transport select jtag

# Source the target configuration for the STM32H7 series.
source [find target/stm32h7x.cfg]

# (Recommended for initial bring-up) Lower the adapter speed.
adapter speed 1000

This minimal configuration tells OpenOCD to use the standard jlink.cfg and stm32h7x.cfg files. Starting with a lower clock speed (adapter speed 1000 sets it to 1 MHz) is a classic troubleshooting technique to ensure a stable connection before increasing speed for better performance.

Common Failure Mode: A frequent error is Error: couldn't find a configured flash bank. This almost always points to a physical connection issue or a mismatch between the selected target/*.cfg file and the actual hardware. Before diving into complex software issues, always re-verify the physical layer and configuration file accuracy.

Connecting GDB for Source-Level Debugging

Once OpenOCD connects to the target, it starts a server listening for a debugger—typically GDB—on port 3333. From a separate terminal, you connect GDB to this server:

gdb-multiarch -q your_firmware.elf -ex "target extended-remote localhost:3333"

Using gdb-multiarch is crucial for handling various target architectures. The -ex flag executes the connection command upon startup. At this point, you have full programmatic control over the CPU.

Integrating with VS Code for a Seamless Workflow

Modern IDEs like VS Code or Eclipse can automate this entire process into a one-click action. A launch.json file in VS Code can be configured to:

• Define the path to your GDB executable.
• Specify the firmware .elf file containing the debug symbols.
• Run a “pre-launch task” that automatically starts the OpenOCD server.
• Attach the debugger to the GDB server on localhost:3333.

This integration enables true source-level debugging: set breakpoints in your C/C++ code, hover over variables to see their values, inspect memory, and step through execution line by line. It unifies disparate command-line tools into a powerful, cohesive system. This level of integration empowers a single-threaded technical ownership model, allowing individual engineers to solve complex problems end-to-end.

Core JTAG Debugging Workflows in Practice

With a configured toolchain, you can move from guessing about silicon behavior to directly observing and controlling it. These workflows provide the surgical precision needed to diagnose bugs that are otherwise invisible.

The unique power of JTAG is its ability to non-intrusively halt a live system without altering the code. Forget printf debugging and recompiling. JTAG lets you freeze the processor at any moment to see exactly what went wrong, as it happened.

Halting, Stepping, and Inspecting

The most fundamental JTAG workflow begins with halting the CPU. A simple halt command in GDB freezes the processor, providing a complete snapshot of the system state.

Once halted, the investigation begins:

• Inspect CPU Registers: View the contents of all core registers to see the processor’s state at the moment of the halt.
• Examine Memory: Dump any region of RAM or memory-mapped peripheral registers. Are clock configuration registers correct? Is a DMA buffer filled with valid data?
• Analyze the Call Stack: The backtrace command is your most powerful tool for diagnosing crashes. It reveals the sequence of function calls that led to the fault, often pointing directly to the root cause.

From this frozen state, you can single-step through your code line by line (step or next in GDB) or even instruction by instruction (stepi) to observe program flow with high granularity.

Advanced Breakpoints and Watchpoints

Manual halting is useful, but the real efficiency comes from automation. A software breakpoint automatically halts execution when the program counter hits a specific line of code.

For hardware-related bugs, the hardware watchpoint is the definitive tool. This instructs the CPU’s debug logic to halt execution whenever a specific memory address is read from or written to. This is the ultimate weapon for tracking down elusive memory corruption bugs.

Consider these use cases:

• Stack Overflows: Set a watchpoint just beyond the allocated end of the stack. The system will halt the instant an overflow occurs, revealing the offending function call.
• Buffer Overruns: If you suspect a function is writing past an array’s boundary, set a watchpoint on the memory location immediately following that array.
• Corrupted Global Variables: If a critical configuration variable is being modified unexpectedly, a watchpoint will break execution the moment it’s written, revealing the culprit.

These hardware-level capabilities are what separate JTAG from software-only debugging. They provide a level of visibility that is impossible to achieve otherwise.

I once worked with a team that spent a week chasing a bug where an ADC configuration register was being mysteriously overwritten, causing noisy sensor readings. After connecting with JTAG, we set a hardware watchpoint on the register’s address. Within minutes, the debugger halted on a rogue pointer write inside a completely unrelated interrupt service routine—a bug they never would have found with logging alone.

Programming Flash Memory

Beyond debugging, JTAG is essential for initial firmware programming, especially on a fresh prototype with no bootloader. JTAG is often the only mechanism to write the compiled firmware binary (.bin or .hex) into the MCU’s on-chip flash or an external SPI flash.

In OpenOCD, a command like program your_firmware.elf verify reset exit handles the entire process: it erases the necessary sectors, programs the new image, verifies the contents, and resets the CPU. This capability is also critical for recovering “bricked” devices where a bad firmware update has corrupted the bootloader.

This cycle of reliably programming and then immediately debugging is a cornerstone of an effective firmware verification strategy.

Common GDB Commands for JTAG Debugging

This quick reference table lists essential GDB commands for JTAG debugging. Fluency with these is key to efficiency.

Mastering these workflows allows your team to find and fix the most stubborn bugs with precision, reducing rework and shortening the prototype-to-production timeline.

Advanced JTAG Use Cases for Production Systems

While JTAG is the go-to tool for initial bring-up, its value extends to tackling the complexities of production-ready systems. As designs evolve from simple MCUs to intricate, multi-core Systems on Chip (SoCs), your debug strategy must mature as well.

A major challenge with modern SoCs is debugging multiple cores, especially when they occupy separate power domains. A traditional JTAG setup can fail if one core powers down, breaking the scan chain and leaving you blind.

Debugging Multi-Core and Asymmetric Systems

ARM’s CoreSight architecture solves this problem by decoupling debug access from the power state of individual cores. CoreSight uses a single JTAG or SWD access point to communicate with a memory-mapped Debug Access Port (DAP). The DAP acts as a gateway to an on-chip network of debug components, allowing you to reach any core’s debug logic even if other cores are powered down. This capability was a huge leap forward, as detailed in this history of microprocessor debug from embedded.com.

In your OpenOCD configuration, you define each core as a separate target. This allows you to connect a GDB instance to a specific core by targeting a different TCP/IP port, giving you independent control to halt, step, and inspect one core while others continue to run.

JTAG for Manufacturing Test and DFT

Beyond debugging, JTAG’s original purpose was boundary scan testing. This remains a cornerstone of Design for Testability (DFT) and is critical for validating manufacturing quality. By daisy-chaining the JTAG ports of multiple ICs (CPU, FPGAs, CPLDs), you create a unified scan chain for the entire board.

This enables a test fixture to:

• Verify Pin-to-Pin Connectivity: Check for opens and shorts between IC pins without needing physical test points on every net. This is invaluable for detecting defects under BGA packages.
• Test Non-JTAG Components: Drive the I/O pins of a JTAG-enabled chip to test adjacent components like memory or connectors that lack JTAG.
• Program Devices in Parallel: Use the boundary scan chain to flash firmware or configuration data into multiple chips at once, streamlining production.

A well-defined boundary scan test plan dramatically reduces manufacturing test time and cost. It allows you to catch subtle assembly defects like faulty solder joints under a BGA—defects that are impossible to find with visual inspection or a simple functional test.

Securing JTAG Access in Production

An active JTAG port on a production device is a major security vulnerability. It provides a low-level backdoor for reverse engineering firmware, extracting security keys, and cloning your product. A clear strategy for managing this risk is non-negotiable. The decision is a trade-off between security and serviceability.

Common strategies include:

• Blowing eFuses: Permanently disable the JTAG port by blowing on-chip security fuses. This is the most secure option but makes failure analysis on returned units impossible.
• Physical Obfuscation: Remove the physical header from the production PCB, leaving only unpopulated pads. Gaining access requires skilled soldering, which deters casual attacks but allows your team to perform diagnostics.
• Challenge-Response Authentication: Implement a secure bootloader that requires a cryptographically signed token to unlock JTAG. This provides robust security while enabling authorized field service.

Choosing the right path requires weighing your product’s security requirements against your long-term support plans. For a deeper discussion, read our guide on the principles of security in embedded systems.

Answering Your JTAG Questions

Here are answers to common questions teams face when implementing JTAG debugging.

JTAG vs. SWD: Which One and When?

JTAG is the classic 4- or 5-wire interface (TDI, TDO, TCK, TMS, and optional TRST). SWD (Serial Wire Debug) is a newer, two-wire protocol from ARM (SWDIO and SWCLK).

Recommendation:

• Use SWD for day-to-day firmware debugging on ARM Cortex-M MCUs. It saves PCB space and is highly efficient.
• Use JTAG for:
  • Boundary Scan Testing: Required for manufacturing tests to check board-level connectivity. SWD cannot do this.
  • Multi-Device Chains: JTAG was designed to daisy-chain multiple chips (FPGAs, CPLDs, SoCs) on a single bus.
  • Non-ARM Architectures: JTAG is an IEEE standard supported by a vast range of processors and FPGAs.

Many ARM chips support both protocols on shared pins, offering the best of both worlds.

How Do I Fix a Stubborn Connection Failure?

When a JTAG connection fails, methodically check for the most common failure modes before assuming a complex hardware fault.

Common Mistakes Checklist:

1. Physical Layer: Is the target board powered on? Are ribbon cable headers fully seated and oriented correctly? Is the pinout 100% correct?
2. Voltage Reference: Is the probe’s Vref pin correctly connected to the target’s VCC? A missing Vref is a top cause of connection failure.
3. Signal Integrity: Is the JTAG ribbon cable too long (>15 cm)? Long cables are prone to noise. Try the shortest cable you have.
4. Clock Speed: Is the TCK speed too high for the board layout? In your OpenOCD script, lower the clock by adding adapter speed 1000 (for 1 MHz). A stable connection at low speed indicates a signal integrity problem.
5. Software Configuration: Is there a typo in your openocd.cfg? Are you sourcing the correct interface/*.cfg and target/*.cfg files?

I have seen teams lose half a day to a “hardware bug” that was just a copy-paste error in a config file. Always assume the simplest thing failed first. Your software setup is as critical as your wiring.

What Are the Security Risks of Leaving JTAG Enabled?

Leaving an open JTAG port on a production device is a critical security vulnerability. An attacker with physical access can use a debugger to:

• Dump the entire firmware binary from flash.
• Reverse-engineer your proprietary algorithms.
• Extract security keys, certificates, or other sensitive data.
• Clone the device.

For any product with valuable IP, securing the debug port is mandatory. The strategy is a trade-off between security and serviceability.

1. Blow Security Fuses: The most secure method. Most MCUs have one-time programmable fuses to permanently disable the debug interface. Trade-off: This makes it impossible to perform failure analysis on field returns.
2. Remove the Connector: A good balance. The production PCB is designed with unpopulated pads for the JTAG header. This physical barrier stops casual attackers but allows your team to solder on a connector for diagnostics.
3. Implement Authenticated Access: The most flexible solution. The bootloader requires a cryptographically signed “unlock” command to enable the JTAG port. This provides strong security while allowing authorized access for field service.

Choosing the right strategy depends on your product’s security posture and long-term failure analysis goals.

At Sheridan Technologies, we help teams build robust design-for-testability and security strategies from the start. Getting these details right early minimizes program risk and ensures a smooth path to production. If you’re navigating the complexities of hardware bring-up, a strategic design review can make all the difference.

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